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    <title>tyler-jurgens Tracker</title>
    <link>https://communities.vmware.com/wbsdv95928/tracker</link>
    <description>tyler-jurgens Tracker</description>
    <pubDate>Wed, 15 Nov 2023 09:05:46 GMT</pubDate>
    <dc:date>2023-11-15T09:05:46Z</dc:date>
    <item>
      <title>Enabling IEEE mode for vSAN RDMA</title>
      <link>https://communities.vmware.com/t5/ESXi-Discussions/Enabling-IEEE-mode-for-vSAN-RDMA/m-p/2989376#M290385</link>
      <description>&lt;P&gt;We’re trying to enable RDMA on vSAN 8 (vCenter: 8.0.1 build: 21860503, VMware ESXi, 8.0.1, 21813344) with our ConnextX5 NICs but running into challenges getting everything configured.&lt;/P&gt;&lt;P&gt;No matter what we configure, we can’t get our NIC to show “Mode: 3 - IEEE mode”. It remains in Mode: 0 - Unknown.&lt;/P&gt;&lt;PRE&gt;[&lt;SPAN class=""&gt;root@1:~&lt;/SPAN&gt;] &lt;SPAN class=""&gt;esxcli&lt;/SPAN&gt; &lt;SPAN class=""&gt;network&lt;/SPAN&gt; &lt;SPAN class=""&gt;nic&lt;/SPAN&gt; &lt;SPAN class=""&gt;dcb&lt;/SPAN&gt; &lt;SPAN class=""&gt;status&lt;/SPAN&gt; &lt;SPAN class=""&gt;get&lt;/SPAN&gt; &lt;SPAN class=""&gt;-n&lt;/SPAN&gt; &lt;SPAN class=""&gt;vmnic0&lt;/SPAN&gt;
   &lt;SPAN class=""&gt;Nic Name:&lt;/SPAN&gt; &lt;SPAN class=""&gt;vmnic0&lt;/SPAN&gt;
   &lt;SPAN class=""&gt;Mode:&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;-&lt;/SPAN&gt; &lt;SPAN class=""&gt;Unknown&lt;/SPAN&gt;
   &lt;SPAN class=""&gt;Enabled:&lt;/SPAN&gt; &lt;SPAN class=""&gt;true&lt;/SPAN&gt;
   &lt;SPAN class=""&gt;Capabilities:&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Priority Group:&lt;/SPAN&gt; &lt;SPAN class=""&gt;true&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Priority Flow Control:&lt;/SPAN&gt; &lt;SPAN class=""&gt;true&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;PG Traffic Classes:&lt;/SPAN&gt; &lt;SPAN class=""&gt;8&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;PFC Traffic Classes:&lt;/SPAN&gt; &lt;SPAN class=""&gt;8&lt;/SPAN&gt;
   &lt;SPAN class=""&gt;PFC Enabled:&lt;/SPAN&gt; &lt;SPAN class=""&gt;true&lt;/SPAN&gt;
   &lt;SPAN class=""&gt;PFC Configuration:&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;1&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
   &lt;SPAN class=""&gt;IEEE ETS Configuration:&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Willing Bit In ETS Config TLV:&lt;/SPAN&gt; &lt;SPAN class=""&gt;1&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Supported Capacity:&lt;/SPAN&gt; &lt;SPAN class=""&gt;8&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Credit Based Shaper ETS Algorithm Supported:&lt;/SPAN&gt; &lt;SPAN class=""&gt;0x0&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;TX Bandwidth Per TC:&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;RX Bandwidth Per TC:&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;TSA Assignment Table Per TC:&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Priority Assignment Per TC:&lt;/SPAN&gt; &lt;SPAN class=""&gt;1&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;3&lt;/SPAN&gt; &lt;SPAN class=""&gt;4&lt;/SPAN&gt; &lt;SPAN class=""&gt;5&lt;/SPAN&gt; &lt;SPAN class=""&gt;6&lt;/SPAN&gt; &lt;SPAN class=""&gt;7&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Recommended TC Bandwidth Per TC:&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;13&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt; &lt;SPAN class=""&gt;12&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Recommended TSA Assignment Per TC:&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Recommended Priority Assignment Per TC:&lt;/SPAN&gt; &lt;SPAN class=""&gt;1&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;2&lt;/SPAN&gt; &lt;SPAN class=""&gt;3&lt;/SPAN&gt; &lt;SPAN class=""&gt;4&lt;/SPAN&gt; &lt;SPAN class=""&gt;5&lt;/SPAN&gt; &lt;SPAN class=""&gt;6&lt;/SPAN&gt; &lt;SPAN class=""&gt;7&lt;/SPAN&gt;
   &lt;SPAN class=""&gt;IEEE PFC Configuration:&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Number Of Traffic Classes:&lt;/SPAN&gt; &lt;SPAN class=""&gt;8&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;PFC Configuration:&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Macsec Bypass Capability Is Enabled:&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Round Trip Propagation Delay Of Link:&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Sent PFC Frames:&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         &lt;SPAN class=""&gt;Received PFC Frames:&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt; &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
   &lt;SPAN class=""&gt;DCB Apps:&lt;/SPAN&gt;
&lt;/PRE&gt;&lt;P&gt;I’ve configured the NIC and ESXi like this:&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;/&lt;/SPAN&gt;opt&lt;SPAN class=""&gt;/&lt;/SPAN&gt;mellanox&lt;SPAN class=""&gt;/&lt;/SPAN&gt;bin&lt;SPAN class=""&gt;/&lt;/SPAN&gt;mlxconfig &lt;SPAN class=""&gt;-&lt;/SPAN&gt;d mt4119_pciconf0 &lt;SPAN class=""&gt;set&lt;/SPAN&gt; DCBX_IEEE_P1&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;SPAN class=""&gt;1&lt;/SPAN&gt; DCBX_CEE_P1&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;SPAN class=""&gt;0&lt;/SPAN&gt; DCBX_IEEE_P2&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;SPAN class=""&gt;1&lt;/SPAN&gt; DCBX_CEE_P2&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;SPAN class=""&gt;0&lt;/SPAN&gt; LLDP_NB_DCBX_P1&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;SPAN class=""&gt;1&lt;/SPAN&gt; LLDP_NB_DCBX_P2&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;SPAN class=""&gt;1&lt;/SPAN&gt;

esxcli &lt;SPAN class=""&gt;system&lt;/SPAN&gt; &lt;SPAN class=""&gt;module&lt;/SPAN&gt; parameters &lt;SPAN class=""&gt;set&lt;/SPAN&gt; &lt;SPAN class=""&gt;-&lt;/SPAN&gt;m nmlx5_core &lt;SPAN class=""&gt;-&lt;/SPAN&gt;p dcbx&lt;SPAN class=""&gt;=&lt;/SPAN&gt;&lt;SPAN class=""&gt;1&lt;/SPAN&gt;

esxcli &lt;SPAN class=""&gt;system&lt;/SPAN&gt; &lt;SPAN class=""&gt;module&lt;/SPAN&gt; parameters &lt;SPAN class=""&gt;set&lt;/SPAN&gt; &lt;SPAN class=""&gt;-&lt;/SPAN&gt;m nmlx5_core &lt;SPAN class=""&gt;-&lt;/SPAN&gt;p "pfctx=0x08 pfcrx=0x08 trust_state=2 max_vfs=4"

esxcli &lt;SPAN class=""&gt;system&lt;/SPAN&gt; &lt;SPAN class=""&gt;module&lt;/SPAN&gt; parameters &lt;SPAN class=""&gt;set&lt;/SPAN&gt; &lt;SPAN class=""&gt;-&lt;/SPAN&gt;m nmlx5_rdma &lt;SPAN class=""&gt;-&lt;/SPAN&gt;p "pcp_force=3 dscp_force=26"&lt;/PRE&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;[root@1:~]&lt;/SPAN&gt; /opt/mellanox/bin/mlxconfig -d mt4119_pciconf0 query

Device &lt;SPAN class=""&gt;#1&lt;/SPAN&gt;:
----------

Device type:    ConnectX5
Name:           &lt;SPAN class=""&gt;879482&lt;/SPAN&gt;-B21_Ax
Description:    HPE InfiniBand FDR/Ethernet &lt;SPAN class=""&gt;40&lt;/SPAN&gt;/&lt;SPAN class=""&gt;50&lt;/SPAN&gt;Gb &lt;SPAN class=""&gt;2&lt;/SPAN&gt;-port &lt;SPAN class=""&gt;547&lt;/SPAN&gt;FLR-QSFP Adapter
Device:         mt4119_pciconf0

Configurations:                                      Next Boot
         MEMIC_BAR_SIZE                              &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         MEMIC_SIZE_LIMIT                            &lt;SPAN class=""&gt;_256KB&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         HOST_CHAINING_MODE                          &lt;SPAN class=""&gt;DISABLED&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         HOST_CHAINING_CACHE_DISABLE                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         HOST_CHAINING_DESCRIPTORS                   Array[&lt;SPAN class=""&gt;0&lt;/SPAN&gt;..&lt;SPAN class=""&gt;7&lt;/SPAN&gt;]
         HOST_CHAINING_TOTAL_BUFFER_SIZE             Array[&lt;SPAN class=""&gt;0&lt;/SPAN&gt;..&lt;SPAN class=""&gt;7&lt;/SPAN&gt;]
         FLEX_PARSER_PROFILE_ENABLE                  &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         FLEX_IPV4_OVER_VXLAN_PORT                   &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         ROCE_NEXT_PROTOCOL                          &lt;SPAN class=""&gt;254&lt;/SPAN&gt;
         ESWITCH_HAIRPIN_DESCRIPTORS                 Array[&lt;SPAN class=""&gt;0&lt;/SPAN&gt;..&lt;SPAN class=""&gt;7&lt;/SPAN&gt;]
         ESWITCH_HAIRPIN_TOT_BUFFER_SIZE             Array[&lt;SPAN class=""&gt;0&lt;/SPAN&gt;..&lt;SPAN class=""&gt;7&lt;/SPAN&gt;]
         PF_BAR2_SIZE                                &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         PF_NUM_OF_VF_VALID                          &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         NON_PREFETCHABLE_PF_BAR                     &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         VF_VPD_ENABLE                               &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PF_NUM_PF_MSIX_VALID                        &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PER_PF_NUM_SF                               &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         STRICT_VF_MSIX_NUM                          &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         VF_NODNIC_ENABLE                            &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         NUM_PF_MSIX_VALID                           &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         NUM_OF_VFS                                  &lt;SPAN class=""&gt;8&lt;/SPAN&gt;
         NUM_OF_PF                                   &lt;SPAN class=""&gt;2&lt;/SPAN&gt;
         PF_BAR2_ENABLE                              &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         SRIOV_EN                                    &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         PF_LOG_BAR_SIZE                             &lt;SPAN class=""&gt;5&lt;/SPAN&gt;
         VF_LOG_BAR_SIZE                             &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         NUM_PF_MSIX                                 &lt;SPAN class=""&gt;63&lt;/SPAN&gt;
         NUM_VF_MSIX                                 &lt;SPAN class=""&gt;11&lt;/SPAN&gt;
         INT_LOG_MAX_PAYLOAD_SIZE                    &lt;SPAN class=""&gt;AUTOMATIC&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PCIE_CREDIT_TOKEN_TIMEOUT                   &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         ACCURATE_TX_SCHEDULER                       &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PARTIAL_RESET_EN                            &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         SW_RECOVERY_ON_ERRORS                       &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         RESET_WITH_HOST_ON_ERRORS                   &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         ADVANCED_POWER_SETTINGS                     &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         CQE_COMPRESSION                             &lt;SPAN class=""&gt;BALANCED&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         IP_OVER_VXLAN_EN                            &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         MKEY_BY_NAME                                &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         ESWITCH_IPV4_TTL_MODIFY_ENABLE              &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PRIO_TAG_REQUIRED_EN                        &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         UCTX_EN                                     &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         PCI_ATOMIC_MODE                             &lt;SPAN class=""&gt;PCI_ATOMIC_DISABLED_EXT_ATOMIC_ENABLED&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         TUNNEL_ECN_COPY_DISABLE                     &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         LRO_LOG_TIMEOUT0                            &lt;SPAN class=""&gt;6&lt;/SPAN&gt;
         LRO_LOG_TIMEOUT1                            &lt;SPAN class=""&gt;7&lt;/SPAN&gt;
         LRO_LOG_TIMEOUT2                            &lt;SPAN class=""&gt;8&lt;/SPAN&gt;
         LRO_LOG_TIMEOUT3                            &lt;SPAN class=""&gt;13&lt;/SPAN&gt;
         LOG_TX_PSN_WINDOW                           &lt;SPAN class=""&gt;7&lt;/SPAN&gt;
         LOG_MAX_OUTSTANDING_WQE                     &lt;SPAN class=""&gt;7&lt;/SPAN&gt;
         ROCE_ADAPTIVE_ROUTING_EN                    &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         TUNNEL_IP_PROTO_ENTROPY_DISABLE             &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         ICM_CACHE_MODE                              &lt;SPAN class=""&gt;DEVICE_DEFAULT&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         TX_SCHEDULER_BURST                          &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         ZERO_TOUCH_TUNING_ENABLE                    &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         LOG_MAX_QUEUE                               &lt;SPAN class=""&gt;17&lt;/SPAN&gt;
         LOG_DCR_HASH_TABLE_SIZE                     &lt;SPAN class=""&gt;11&lt;/SPAN&gt;
         MAX_PACKET_LIFETIME                         &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         DCR_LIFO_SIZE                               &lt;SPAN class=""&gt;16384&lt;/SPAN&gt;
         LINK_TYPE_P1                                &lt;SPAN class=""&gt;ETH&lt;/SPAN&gt;(&lt;SPAN class=""&gt;2&lt;/SPAN&gt;)
         LINK_TYPE_P2                                &lt;SPAN class=""&gt;ETH&lt;/SPAN&gt;(&lt;SPAN class=""&gt;2&lt;/SPAN&gt;)
         ROCE_CC_PRIO_MASK_P1                        &lt;SPAN class=""&gt;255&lt;/SPAN&gt;
         ROCE_CC_PRIO_MASK_P2                        &lt;SPAN class=""&gt;255&lt;/SPAN&gt;
         CLAMP_TGT_RATE_AFTER_TIME_INC_P1            &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         CLAMP_TGT_RATE_P1                           &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         RPG_TIME_RESET_P1                           &lt;SPAN class=""&gt;300&lt;/SPAN&gt;
         RPG_BYTE_RESET_P1                           &lt;SPAN class=""&gt;32767&lt;/SPAN&gt;
         RPG_THRESHOLD_P1                            &lt;SPAN class=""&gt;1&lt;/SPAN&gt;
         RPG_MAX_RATE_P1                             &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         RPG_AI_RATE_P1                              &lt;SPAN class=""&gt;5&lt;/SPAN&gt;
         RPG_HAI_RATE_P1                             &lt;SPAN class=""&gt;50&lt;/SPAN&gt;
         RPG_GD_P1                                   &lt;SPAN class=""&gt;11&lt;/SPAN&gt;
         RPG_MIN_DEC_FAC_P1                          &lt;SPAN class=""&gt;50&lt;/SPAN&gt;
         RPG_MIN_RATE_P1                             &lt;SPAN class=""&gt;1&lt;/SPAN&gt;
         RATE_TO_SET_ON_FIRST_CNP_P1                 &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         DCE_TCP_G_P1                                &lt;SPAN class=""&gt;1019&lt;/SPAN&gt;
         DCE_TCP_RTT_P1                              &lt;SPAN class=""&gt;1&lt;/SPAN&gt;
         RATE_REDUCE_MONITOR_PERIOD_P1               &lt;SPAN class=""&gt;4&lt;/SPAN&gt;
         INITIAL_ALPHA_VALUE_P1                      &lt;SPAN class=""&gt;1023&lt;/SPAN&gt;
         MIN_TIME_BETWEEN_CNPS_P1                    &lt;SPAN class=""&gt;4&lt;/SPAN&gt;
         CNP_802P_PRIO_P1                            &lt;SPAN class=""&gt;6&lt;/SPAN&gt;
         CNP_DSCP_P1                                 &lt;SPAN class=""&gt;48&lt;/SPAN&gt;
         CLAMP_TGT_RATE_AFTER_TIME_INC_P2            &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         CLAMP_TGT_RATE_P2                           &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         RPG_TIME_RESET_P2                           &lt;SPAN class=""&gt;300&lt;/SPAN&gt;
         RPG_BYTE_RESET_P2                           &lt;SPAN class=""&gt;32767&lt;/SPAN&gt;
         RPG_THRESHOLD_P2                            &lt;SPAN class=""&gt;1&lt;/SPAN&gt;
         RPG_MAX_RATE_P2                             &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         RPG_AI_RATE_P2                              &lt;SPAN class=""&gt;5&lt;/SPAN&gt;
         RPG_HAI_RATE_P2                             &lt;SPAN class=""&gt;50&lt;/SPAN&gt;
         RPG_GD_P2                                   &lt;SPAN class=""&gt;11&lt;/SPAN&gt;
         RPG_MIN_DEC_FAC_P2                          &lt;SPAN class=""&gt;50&lt;/SPAN&gt;
         RPG_MIN_RATE_P2                             &lt;SPAN class=""&gt;1&lt;/SPAN&gt;
         RATE_TO_SET_ON_FIRST_CNP_P2                 &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         DCE_TCP_G_P2                                &lt;SPAN class=""&gt;1019&lt;/SPAN&gt;
         DCE_TCP_RTT_P2                              &lt;SPAN class=""&gt;1&lt;/SPAN&gt;
         RATE_REDUCE_MONITOR_PERIOD_P2               &lt;SPAN class=""&gt;4&lt;/SPAN&gt;
         INITIAL_ALPHA_VALUE_P2                      &lt;SPAN class=""&gt;1023&lt;/SPAN&gt;
         MIN_TIME_BETWEEN_CNPS_P2                    &lt;SPAN class=""&gt;4&lt;/SPAN&gt;
         CNP_802P_PRIO_P2                            &lt;SPAN class=""&gt;6&lt;/SPAN&gt;
         CNP_DSCP_P2                                 &lt;SPAN class=""&gt;48&lt;/SPAN&gt;
         LLDP_NB_DCBX_P1                             &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         LLDP_NB_RX_MODE_P1                          &lt;SPAN class=""&gt;ALL&lt;/SPAN&gt;(&lt;SPAN class=""&gt;2&lt;/SPAN&gt;)
         LLDP_NB_TX_MODE_P1                          &lt;SPAN class=""&gt;ALL&lt;/SPAN&gt;(&lt;SPAN class=""&gt;2&lt;/SPAN&gt;)
         LLDP_NB_DCBX_P2                             &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         LLDP_NB_RX_MODE_P2                          &lt;SPAN class=""&gt;ALL&lt;/SPAN&gt;(&lt;SPAN class=""&gt;2&lt;/SPAN&gt;)
         LLDP_NB_TX_MODE_P2                          &lt;SPAN class=""&gt;ALL&lt;/SPAN&gt;(&lt;SPAN class=""&gt;2&lt;/SPAN&gt;)
         ROCE_RTT_RESP_DSCP_P1                       &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         ROCE_RTT_RESP_DSCP_MODE_P1                  &lt;SPAN class=""&gt;DEVICE_DEFAULT&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         ROCE_RTT_RESP_DSCP_P2                       &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         ROCE_RTT_RESP_DSCP_MODE_P2                  &lt;SPAN class=""&gt;DEVICE_DEFAULT&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         DCBX_IEEE_P1                                &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         DCBX_CEE_P1                                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         DCBX_WILLING_P1                             &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         DCBX_IEEE_P2                                &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         DCBX_CEE_P2                                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         DCBX_WILLING_P2                             &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         KEEP_ETH_LINK_UP_P1                         &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         KEEP_IB_LINK_UP_P1                          &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         KEEP_LINK_UP_ON_BOOT_P1                     &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         KEEP_LINK_UP_ON_STANDBY_P1                  &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         DO_NOT_CLEAR_PORT_STATS_P1                  &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         AUTO_POWER_SAVE_LINK_DOWN_P1                &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         KEEP_ETH_LINK_UP_P2                         &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         KEEP_IB_LINK_UP_P2                          &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         KEEP_LINK_UP_ON_BOOT_P2                     &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         KEEP_LINK_UP_ON_STANDBY_P2                  &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         DO_NOT_CLEAR_PORT_STATS_P2                  &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         AUTO_POWER_SAVE_LINK_DOWN_P2                &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         NUM_OF_VL_P1                                &lt;SPAN class=""&gt;_4_VLs&lt;/SPAN&gt;(&lt;SPAN class=""&gt;3&lt;/SPAN&gt;)
         NUM_OF_TC_P1                                &lt;SPAN class=""&gt;_8_TCs&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         NUM_OF_PFC_P1                               &lt;SPAN class=""&gt;8&lt;/SPAN&gt;
         VL15_BUFFER_SIZE_P1                         &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         QOS_TRUST_STATE_P1                          &lt;SPAN class=""&gt;TRUST_PCP&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         NUM_OF_VL_P2                                &lt;SPAN class=""&gt;_4_VLs&lt;/SPAN&gt;(&lt;SPAN class=""&gt;3&lt;/SPAN&gt;)
         NUM_OF_TC_P2                                &lt;SPAN class=""&gt;_8_TCs&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         NUM_OF_PFC_P2                               &lt;SPAN class=""&gt;8&lt;/SPAN&gt;
         VL15_BUFFER_SIZE_P2                         &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         QOS_TRUST_STATE_P2                          &lt;SPAN class=""&gt;TRUST_PCP&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         DUP_MAC_ACTION_P1                           &lt;SPAN class=""&gt;LAST_CFG&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         MPFS_MC_LOOPBACK_DISABLE_P1                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         MPFS_UC_LOOPBACK_DISABLE_P1                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         UNKNOWN_UPLINK_MAC_FLOOD_P1                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         SRIOV_IB_ROUTING_MODE_P1                    &lt;SPAN class=""&gt;LID&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         IB_ROUTING_MODE_P1                          &lt;SPAN class=""&gt;LID&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         DUP_MAC_ACTION_P2                           &lt;SPAN class=""&gt;LAST_CFG&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         MPFS_MC_LOOPBACK_DISABLE_P2                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         MPFS_UC_LOOPBACK_DISABLE_P2                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         UNKNOWN_UPLINK_MAC_FLOOD_P2                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         SRIOV_IB_ROUTING_MODE_P2                    &lt;SPAN class=""&gt;LID&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         IB_ROUTING_MODE_P2                          &lt;SPAN class=""&gt;LID&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         PHY_AUTO_NEG_P1                             &lt;SPAN class=""&gt;DEVICE_DEFAULT&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PHY_RATE_MASK_OVERRIDE_P1                   &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PHY_FEC_OVERRIDE_P1                         &lt;SPAN class=""&gt;DEVICE_DEFAULT&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PHY_AUTO_NEG_P2                             &lt;SPAN class=""&gt;DEVICE_DEFAULT&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PHY_RATE_MASK_OVERRIDE_P2                   &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PHY_FEC_OVERRIDE_P2                         &lt;SPAN class=""&gt;DEVICE_DEFAULT&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PF_TOTAL_SF                                 &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         PF_SF_BAR_SIZE                              &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         PF_NUM_PF_MSIX                              &lt;SPAN class=""&gt;63&lt;/SPAN&gt;
         ROCE_CONTROL                                &lt;SPAN class=""&gt;ROCE_ENABLE&lt;/SPAN&gt;(&lt;SPAN class=""&gt;2&lt;/SPAN&gt;)
         PCI_WR_ORDERING                             &lt;SPAN class=""&gt;per_mkey&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         MULTI_PORT_VHCA_EN                          &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         PORT_OWNER                                  &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         ALLOW_RD_COUNTERS                           &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         RENEG_ON_CHANGE                             &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         TRACER_ENABLE                               &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         IP_VER                                      &lt;SPAN class=""&gt;IPv4&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         BOOT_UNDI_NETWORK_WAIT                      &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         UEFI_HII_EN                                 &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         BOOT_DBG_LOG                                &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         UEFI_LOGS                                   &lt;SPAN class=""&gt;DISABLED&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         BOOT_VLAN                                   &lt;SPAN class=""&gt;1&lt;/SPAN&gt;
         LEGACY_BOOT_PROTOCOL                        &lt;SPAN class=""&gt;PXE&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         BOOT_INTERRUPT_DIS                          &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         BOOT_LACP_DIS                               &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         BOOT_VLAN_EN                                &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         BOOT_PKEY                                   &lt;SPAN class=""&gt;0&lt;/SPAN&gt;
         P2P_ORDERING_MODE                           &lt;SPAN class=""&gt;DEVICE_DEFAULT&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         ATS_ENABLED                                 &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         DYNAMIC_VF_MSIX_TABLE                       &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         EXP_ROM_UEFI_x86_ENABLE                     &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         EXP_ROM_PXE_ENABLE                          &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)
         ADVANCED_PCI_SETTINGS                       &lt;SPAN class=""&gt;False&lt;/SPAN&gt;(&lt;SPAN class=""&gt;0&lt;/SPAN&gt;)
         SAFE_MODE_THRESHOLD                         &lt;SPAN class=""&gt;10&lt;/SPAN&gt;
         SAFE_MODE_ENABLE                            &lt;SPAN class=""&gt;True&lt;/SPAN&gt;(&lt;SPAN class=""&gt;1&lt;/SPAN&gt;)&lt;/PRE&gt;&lt;LI-CODE lang="markup"&gt;2023-10-02T21:50:02.178Z Wa(180) vmkwarning: cpu14:2098420)WARNING: rdmaDriver: RDMAFindTeamDeviceByPortID:3138: Unspported team policy = 8 status = Success
2023-10-02T21:50:02.178Z Wa(180) vmkwarning: cpu14:2098420)WARNING: rdmaDriver: RDMACM_BindLegacy:4297: The provided interface (&amp;lt;redacted&amp;gt;) does not have a registered rdma device.
2023-10-02T21:50:02.178Z In(182) vmkernel: cpu14:2098420)RDT: RDTCreateRDMAServer:2754: vmk_RDMACMBind() failed for server Bad parameter
2023-10-02T21:50:02.178Z In(182) vmkernel: cpu14:2098420)RDT: RDTCreateRDMAServer:2787: RDTCreateRDMAServer() exiting with failure
2023-10-02T21:50:02.178Z In(182) vmkernel: cpu14:2098420)RDT: RDTEnableRdmaInt:642: Failed to create listener for address &amp;lt;redacted&amp;gt;, protocol 2, status Bad parameter
2023-10-02T21:50:07.181Z In(182) vmkernel: cpu14:2098420)RDT: RDTDisableRdmaInt:722: SupportedTransportProtocolsMask removes RDMA
2023-10-02T21:50:07.181Z Wa(180) vmkwarning: cpu14:2098420)WARNING: rdmaDriver: RDMAFindTeamDeviceByPortID:3138: Unspported team policy = 8 status = Success
2023-10-02T21:50:07.181Z Wa(180) vmkwarning: cpu14:2098420)WARNING: rdmaDriver: RDMACM_BindLegacy:4297: The provided interface (&amp;lt;redacted&amp;gt;) does not have a registered rdma device.
2023-10-02T21:50:07.181Z In(182) vmkernel: cpu14:2098420)RDT: RDTCreateRDMAServer:2754: vmk_RDMACMBind() failed for server Bad parameter
2023-10-02T21:50:07.181Z In(182) vmkernel: cpu14:2098420)RDT: RDTCreateRDMAServer:2787: RDTCreateRDMAServer() exiting with failure
2023-10-02T21:50:07.181Z In(182) vmkernel: cpu14:2098420)RDT: RDTEnableRdmaInt:642: Failed to create listener for address &amp;lt;redacted&amp;gt;, protocol 2, status Bad parameter&lt;/LI-CODE&gt;&lt;P&gt;We followed this guide for the switches:&lt;BR /&gt;&lt;A class="" href="https://enterprise-support.nvidia.com/s/article/qos-configuration-examples-for-cisco-nexus-5600" target="_blank" rel="noopener nofollow ugc"&gt;https://enterprise-support.nvidia.com/s/article/qos-configuration-examples-for-cisco-nexus-5600&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class=""&gt;5&lt;/SPAN&gt;&lt;/A&gt;&lt;/P&gt;&lt;P&gt;We also gathered the information from:&lt;BR /&gt;&lt;A class="" href="https://www.reddit.com/r/vmware/comments/ozhq6j/vsan_rdma_with_mellanox_nic/" target="_blank" rel="noopener nofollow ugc"&gt;https://www.reddit.com/r/vmware/comments/ozhq6j/vsan_rdma_with_mellanox_nic/&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN class=""&gt;8&lt;/SPAN&gt;&lt;/A&gt;&lt;/P&gt;&lt;P&gt;Any idea what we may be missing or what else we can try? Everything looks like we should be able to use RDMA, yet here we are.&lt;/P&gt;</description>
      <pubDate>Mon, 02 Oct 2023 21:52:06 GMT</pubDate>
      <guid>https://communities.vmware.com/t5/ESXi-Discussions/Enabling-IEEE-mode-for-vSAN-RDMA/m-p/2989376#M290385</guid>
      <dc:creator>tyler-jurgens</dc:creator>
      <dc:date>2023-10-02T21:52:06Z</dc:date>
    </item>
    <item>
      <title>Aria Operations for Logs: S3 compatible storage for long term log retention</title>
      <link>https://communities.vmware.com/t5/VMware-Aria-Operations-for-Logs/Aria-Operations-for-Logs-S3-compatible-storage-for-long-term-log/m-p/2973872#M2885</link>
      <description>&lt;P&gt;Is there any plan to allow S3 compatible storage buckets for long term log retention? We have a large S3 object storage cluster we would like to use for log retention, but there doesn't seem to be a current way of achieving this goal.&lt;/P&gt;&lt;P&gt;Is it planned for a future release?&lt;/P&gt;</description>
      <pubDate>Tue, 20 Jun 2023 19:28:31 GMT</pubDate>
      <guid>https://communities.vmware.com/t5/VMware-Aria-Operations-for-Logs/Aria-Operations-for-Logs-S3-compatible-storage-for-long-term-log/m-p/2973872#M2885</guid>
      <dc:creator>tyler-jurgens</dc:creator>
      <dc:date>2023-06-20T19:28:31Z</dc:date>
    </item>
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