Have a look the following KB Article VMware KB: vMotion CPU Compatibility - Migrations Prevented Due to CPU Mismatch - How to Override Masks - You will find the features and corresponding mask toward the end, but read the entire article.
The article shows bit masks for SSE3 and up. I am not seeing any information for SSE and SSE2. It is a good read but apparently my scenario is not supported.
Out of curiosity, why do you want to hide these specific instructions? what are you trying to achieve?
Some of our users have CPU's without these instructions and we need to verify that we can run in this environment.
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>>Some of our users have CPU's without these instructions and we need to verify that we can run in this environment.
SSE and SSE2 instruction sets were supported in x86 CPUs that are released around 2000. If your users are having CPUs that will not support SSE and SSE2 instruction sets then those CPUs are not supported by ESXi.
Add the below options in VMX config file of VM to disable the SSE and SSE2 instructions. By adding the below option, guest OS might fail to boot as it might expect SSE and SSE2 feature to be available in CPU.
Confirm with your users to have either disable SSE and SSE2 or SSE4.1 and SSE4.2 instruction sets?
What CPU's are you using? Most CPU in recent history will have SSE. IMHO, unless you are taking advantage of SSE instruction set, you dont really need worry about it. You are just complicating your set up without any benefits.
Visual Studio 2012 projects enable SSE/SSE2 instructions by default. This mean any binary built using standard settings will include use of xmm registers that were not available on old CPU's and crash as a result. What I am trying to achieve is simulate this scenario through virtualization.
In order to ensure that our binaries remain compatible for these customers we need to override this option in the VS project so it does not use those instructions. In addition, testers want to be able to put the product through a full certification in that environment.
Using rajivdp's instructions, I see the utility program CPU-Z now does not report SSE/SSE2 in the instruction set. But I am not sure if what I did is just fooling CPU-Z or if it actually removed those instructions from the CPU. I ran some tests with binaries that were built with SSE/SSE2 instructions and they run fine.
>>Using rajivdp's instructions, I see the utility program CPU-Z now does not report SSE/SSE2 in the instruction set. But I am not sure if what I did is just fooling CPU-Z or if it actually removed those instructions from the CPU.
Above setting will not fool CPU-Z utility.
This above VMX setting will not expose CPUID bits of SSE and SSE2 features to guest OS. When guest boots and try to enumerate what features CPU supports using CPUID instruction, guest OS will not find that SSE and SSE2 instruction set support because we set that bits to zero and therefore guest knew that CPU does not support SSE and SSE2 instructions.
>>ran some tests with binaries that were built with SSE/SSE2 instructions and they run fine.
Did binaries contain any SSE and SSE2 instruction? To my limited knowledge it should throws an exception 6 (Invalid Opcode exception).
Please disassemble and check whether binaries contains any SSE and SSE2 instructions by searching for instructions using XMM registers. For SSE and SSE2 instructions list, follow the link.
Hint for searching SSE and SSE2 instructions:- SSE and SSE2 instructions will use 'XMM' registers, SSE instructions mostly ends with 'S' and SSE2 instruction mostly ends with 'D'.
CPUID masking only changes the features reported by the CPUID instruction. It does not actually remove the instructions from the virtual CPU. However, if the VMM emulates these instructions, it will raise #UD.